14:00-15:40, November 20, 2024
Himawari Room
Session Chair: Prof. Qiang Li, Univ. of Electronic Sci. & Tech. of China (UESTC)
Co-Chair: Hsin-Shu Chen, National Taiwan University
Speakers
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A 2.5-20kSps in-pixel direct digitization front-end for ECoG with in-stimulation recordingEric Fogleman, University of California San Diego, USA
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An 8b 1GS/s SAR ADC with Metastability-based Resolution/Speed Enhancement and Background Calibration Achieving 47.2dB SNDR at Nyquist InputJie Li, Peking University, China
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CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming ProblemsJaydeep Kulkarni, The University of Texas at Austin, USA
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A 0.144 mm2 12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fsRMS Jitter, -271.5dB FoMN, and Sub-10% Jitter VariationXinyu Shen, Chinese Academy of Sciences, China
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A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNsZhaoyang Zhang, Southeast University, China