Plenary Talk 1
Strategy for Semiconductors and the Digital Industry of the Japanese Government (TB Finalize)
Director, IT Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry
TBA
Mr. Hisashi Kanazashi obtained BE degree from Engineering school, the University of Tokyo in 1998, and joined Ministry of International Trade and Industry (now METI), He stayed with Stanford University for a visiting researcher, and obtained MBA from EDHEC(École des hautes études commerciales du Nord) Business School, France. He is now in charge of Japanese governmental policy making in the area including AI and Semiconductor industry.
Plenary Talk 2
Where do Innovations stem from?: Further Innovation Beyond Silicon Technology
President and CEO, LX Semicon Co., Ltd.
In the past few decades, the semiconductor industry has experienced two significant waves of development. The first wave was driven by the innovation of semiconductor devices and process technologies, represented by Moore’s Law. The second wave was driven by system-level innovation, with advancements in silicon technologies such as multi/parallel processing CPU architecture (ILP/TLP), high-performance memory (DDR SDRAM/HBM), high-speed interfaces (SATA/PCIe), and advanced package (SiP/PoP).
However, recently, the innovation driven by silicon and system-level technologies has stagnated, and the semiconductor industry is grappling with issues such as chip size expansion, increased power consumption, and thermal problems. Despite the growth of new markets such as AI, high-performance computing, and EV, these issues may impede the semiconductor industry’s growth. Furthermore, the design tool industry’s consolidation and the high costs of chip manufacturing present significant barriers for new semiconductor companies to thrive.
To overcome these challenges and enter the third wave, deep heterogeneous technologies such as heat dissipation systems, and collaborative innovation will be necessary. This speech will explore the challenges facing the current semiconductor business environment and discuss a wide range of innovations required for the third wave.
Yun-Tae Lee has over 30 years of experience in the semiconductor, display, and electronic components Industries. He received a bachelor’s degree in electrical engineering from Seoul National University in 1983, followed by a master’s degree in semiconductor devices and process from KAIST in 1985. After graduation, he joined Samsung Electronics and began to design chips for communication and industrial systems. In 1994, he obtained Ph.D. in VLSI design for computer architecture from KAIST and returned to System LSI division of the company, laying the foundation for SoC such as network processor and mobile AP. As the VP of the Product Planning Team, he demonstrated his entrepreneurial skills, and as the head of System LSI R&D Department, enhanced the competitiveness of the image sensor, display driver IC, and smart card IC, turning them into the company’s cash cow.
In 2011, he assumed the role of Executive VP of LCD R&D Division at Samsung Display, where he led various innovations solving the critical issues for curved and large-sized panels such as mura and improving a productivity through semiconductor and LCD panel technologies. He was appointed as the CEO of Samsung Electro-Mechanics in 2014, where he ushered in the era of $1 billion in operating profit through productivity innovation in areas such as MLCC, camera module, and package substrate.
In 2020, he officially retired from Samsung Electro-Mechanics. However, after serving as an Executive Advisor for four years, he returned to a semiconductor industry as the CEO of LX Semicon, starting from 2023, with the aim of revitalizing the fabless industry in South Korea.
Plenary Talk 3
Development and Applications of a Memory-Traffic-Efficient Convolutional Neural Network
PhD, Computer Science, University of Illinois at Urbana-Champaign, USA Chair Professor Emeritus, National Tsing Hua University, Taiwan Founder & Chairman, Neuchips Corp., USA & Taiwan
Built upon circuit insight, HarDNet is introduced as an innovative and efficient convolutional neural network architecture aimed at minimizing DRAM access. This design approach leverages the faster speed and lower energy consumption of arithmetic operations compared to DRAM, resulting in significant improvements in accuracy, speed, and energy efficiency. HarDNet’s optimized architecture makes it well-suited for diverse applications including object detection, semantic segmentation, and medical image analysis. As an open-source initiative, HarDNet is accessible for global use and adaptation. Its impact spans various domains and regions, from autonomous driving and industrial automation to vehicle safety, environmental monitoring, colonoscopy polyp segmentation, and MRI imaging. Drawing from deployment insights, this presentation outlines challenges and opportunities in circuit and system design to enable robust and cost-effective deep learning solutions. Additionally, it includes case studies of hardware implementations of HarDNet.
Dr. Youn-Long Lin earned his PhD from the University of Illinois at Urbana-Champaign in 1987. Over 36 years at the National Tsing Hua University, Dr. Lin has developed expertise in physical design automation, high-level synthesis, video codec architecture, and neural network architecture. Beyond academia, he co-founded and served as CTO of Global Unichip Corp, founded Neuchips Corp, and played a pivotal role in establishing the Chip Implementation Center (CIC), fostering collaborative innovation. In an advisory role for the Ministry of Education, Dr. Lin championed VLSI design education programs. His mentorship is reflected in the guidance of 120 Master’s and PhD theses, with many former students recognized as outstanding alumni by the College of Electrical Engineering and Computer Science. Dr. Lin’s multifaceted contributions have significantly shaped academia, industry, and technology.
Plenary Talk 4
Embracing RISC-V, Towards the Era of Open-Source Chip
Deputy Director, Institute of Computing Technology, Chinese Academy of Sciences Chief Scientist, Beijing Institute of Open Source Chip (BOSC)
RISC-V (pronounced “risk five”), known as the fifth generation of reduced instruction set computer (RISC), is an open standard that describes the basic operations a chip can do. RISC-V is selected as one of MIT Technology Review’s 10 Breakthrough Technologies of 2023 for the reason that “a chip design that changes everything”. As an open standard, RISC-V can be used by anyone to design a chip, free of charge. Today, RISC-V has made a significant impact on the chip industry and academia all over the world. In this talk, I will first introduce the status of global RISC-V community and then introduce several RISC-V related projects towards building an open-source chip ecosystem: 1) The XiangShan project targets an open-source high-performance RISC-V core (https://github.com/OpenXiangShan/XiangShan); 2) The iEDA project provides an open-source EDA tool chain; 3) The One Student One Chip (OSOC) Initiative aims to train undergraduates by building real RISC-V chips and has already attracted about 7700 participants from 680+ universities.
Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao co-founded Beijing Institute of Open Source Chip (BOSC). His research interests include computer architecture and computer systems. He is leading the XiangShan project (https://github.com/OpenXiangShan/XiangShan ), which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of RISC-V International Technical Leadership Award, CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.