Special Program - Industry Forum
Chair: Daisuke Mizoguchi, Renesas, Japan
Co-chair: Jihwan Kim, Intel, USA
Industry Forum Talk 1
Technology Trends of Embedded MRAM IP Development for MCUs
Renesas Electronics, Japan
IoT and AI technology are powering a paradigm shift toward a smart society. Microcontroller unit (MCU) plays a major role in a wide range of applications with secure and high-performance operation in home automation, robotics, and medical applications as well as intermittent low-energy operation in IoT endpoint applications. MCUs with embedded flash memory (eFlash) have the advantages in terms of security and faster boot load time without initial program code loading from external flash memories. Endpoint MCUs with eFlash also contribute to low power operation supplied with batteries or energy harvesting sources. On the other hand, it has become increasingly difficult to provide eFlash at advanced technology nodes such as 2Xnm and beyond because of its complex process steps, low affinity with advanced CMOS process, and the need for high-voltage transistors to support 10V-class write/erase voltages. In this presentation, a high-precision boosted cross-coupled sense amplifier, global- and local-trimming with parallel-connected resistors, and cascode-clamp MOS scheme are introduced to achieve random read access frequency of over 200MHz at 125oC. We also present our proposed new technology (a variable parallel bit write scheme and a novel self-termination write scheme) to enhance the advantage of eMRAM, achieving 10.4MB/s fast rewrite throughput and 65-69% lower write energy. These achievements using 2Xnm and/or 1Xnm process technology will enable us to continuously provide advanced MCU products with embedded non-volatile memory to expand new MCU applications.
Takahiro Shimoi received the B.S. and M.S. degrees in physics from Osaka University, Osaka, Japan, in 2010 and 2012, respectively. He joined Renesas Electronics Corporation, Tokyo, Japan, in 2012 and was involved in the development of the embedded split-gate MONOS flash macro for high-end automotive MCUs. He is currently working on the circuit design of embedded MRAM for MCUs.
Industry Forum Talk 2
Photonics-Electronics Convergence Technologies for Computing
NTT Device Innovation Center, NTT Corporation, Japan
Evolution of generative AI is widening the gap between the demand and supply of computing resources and every technological approach is desired to fill the gap. In addition to 3D stacking and heterogeneous integration, optical interconnects is one of the key enablers for scaling out by connecting the LSIs over the reach of conventional electrical interconnects. This also leads to disaggregation of the computing resources, which means fine tuning and reduction of power consumption becomes possible.
In this talk, the trend and R&D efforts on optical devices co-packaged with LSIs will be reviewed from the viewpoints of signal types, packaging technologies and ecosystems. Key indicators of power consumption and shoreline density of optical interfaces will be also explained. Our technology roadmap of Photonics-Electronics Convergence (PEC) Devices will be introduced that includes both package-to-package and die-to-die optical interconnects to enhance I/O capacity of LSIs for computing. This will contribute to realizing Innovative Optical and Wireless Network (IOWN) initiative for future communication infrastructure.
Norio Sato is an Executive Research Engineer and a Group Leader of Research Groups on PEC Devices both in NTT Device Technology Laboratories and NTT Device Innovation Center, NTT Corporation. He received the B.S. and M.S. degrees in physics and the Ph.D. degree in precision engineering from The University of Tokyo. From 1999, he was engaged in the research of MEMS design and fabrication including one-year of visiting research at ETH Switzerland. Since 2010, he was engaged in development of optical switch devices and is currently working on optical transceivers co-packaged with LSIs.
Industry Forum Talk 3
TSMC Design and Technology Platform in state-of-the-art technology
TSMC Design Center, Japan
The TSMC Japan Design Center has been supporting customer design and products through the TSMC Open Innovation Platform. In state-of-the-art technology, Design Technology Co-Optimization (DTCO) involves significant architectural innovation, rather than simply replicating the previous generation’s structure, in order to maximize gains by pushing the limits of the process window. DTCO entails the joint optimization of design and technology parameters for advanced semiconductor devices. During my presentation, we will provide a showcase of an example of Design Technology Co-Optimization at TSMC.
Takuya Yasui currently serves as the Director of TSMC Design Technology Japan, Inc and Design & Technology Platform at Taiwan Semiconductor Manufacturing Co. Ltd. In this role, he is responsible for providing design enablement support to meet the diverse requirements of customers. Since 2020, he has led the TSMC Japan Design Center. He obtained his B.E. degree in electrical engineering and M.E. degree in information engineering from Hiroshima University in 1991 and 1993, respectively. He began his career at Panasonic corporation before joining Socionext, Inc, a joint venture between Fujitsu and Panasonic System LSI business. With over 30 years of professional experience, he has established himself as an expert in physical implementation and design methodology development of System LSI.
Industry Forum Talk 4
Amazing Bodyguard for Integrated Circuits and Microelectronics Systems: ESD Protection Design from Devices to Systems
Amazing Microelectronic Corporation, Taiwan
The scaling trend in the semiconductor industry leads to a reduction in IC component-level ESD robustness. The shift from varistors to TVS for system-level protection indicates that external protection is becoming increasingly important. Amazing Microelectronic has been researching ESD and EOS for more than 20 years and is one of the top companies specializing in ESD protection solutions. With extensive knowledge, experience, and a commitment to staying current with hi-tech trends, Amazing consistently provides the best products to the latest applications. In this talk, I will present the trends and challenges through our showcases.
Ryan Hsin-Chin Jiang is the President of Amazing Microelectronic Corporation, He received his M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1992, and 1998, respectively. He served at the Computer and Communication Research Laboratories (CCL) and SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Taiwan, from 1999 to 2003. He has proposed many inventions to improve reliability and quality of integrated circuits, which have granted 54 U.S. patents and 48 Taiwan patents. He also has published 4 IEEE journal papers and 20 International conference papers. His current research topics include ESD Protection Design, Analog IC Design, Analog Circuits Behavioral Modeling, Hardware Implementation of Neural Network, Semiconductor Device Physics. He has been elected as the President of Taiwan ESD Association from 2005 to 2009, and as Executive Director of BoG from 2011 to 2012.
Industry Forum Talk 5
Silicon Photonic Compute Interconnects for Next-Gen AI/HPC Systems
Intel Labs, USA
We will present in-package silicon photonic (SiPh) transceivers as a technology to address these looming interconnect challenges. This solution leverages HVM-proven SiPh technology platforms with advanced 2.5D/3D packaging to tightly integrate high-bandwidth optical transceivers with host XPUs, offering breakthrough improvements in off-package I/O capability: >5X increase in bandwidth density (vs. pluggable optics) and ~100X increase in reach (vs. all-electrical I/O). Micron-scale SiPh ring resonators – versatile devices that can be configured as modulators and filters – are a key enabler of the proposed solution. By facilitating efficient dense wavelength division multiplexing, they deliver high bandwidth I/O with low footprint. However, their adoption by the industry has been hampered by their extreme sensitivity to process and temperature variations. In particular, we will detail Intel’s demonstration (earlier this year) of CPU-to-CPU optical connectivity using an in-package 4 Tbps SiPh engine chiplet interfacing with the host through PCIe. The 3D-integrated chiplet consists of a SiPh IC that includes integrated 8-wavelength laser and optical amplifiers, and a 22nm CMOS IC with all the necessary RF and control electronics. Finally, we will present potential scaling vectors and remaining challenges for adoption of this exciting new technology.
Ganesh Balamurugan received the B.Tech degree in electronics and communication engineering from Indian Institute of Technology, Madras in 1996, M.S degree in Electrical and Computer Engineering from the University of Texas at Austin in 1998, and Ph.D. degree in EE from the University of Illinois at Urbana-Champaign in 2004. Since 2004, he has been with Intel Corporation working on high-speed wireline communications. His research interests include energy-efficient electrical and optical link design, silicon photonics-based communication circuits, and system level optimization of electro-optical links. He received the IEEE journal of solid-state circuits best paper award in 2021 and is currently a principal engineer at Intel Labs.