A-SSCC 2024

Special Program - Start-up!

11:00-12:40, November 21, 2024
Dahlia 1 Room

Chair: Kyuho Lee, UNIST, Korea
Co-chair: Huai-De Wang, M31 Technology, Taiwan

Start-up! Talk 1

TAI FPGA-based Platform for Real-time AI Computation

Hiroki Nakahara
Hiroki Nakahara

Tokyo Artisan Intelligence
/ Professor, Tohoku University, Japan

With the development of deep learning, the “edge AI” market, including embedded systems, tends to expand. Since edge AI requires large operations under limited computational resources, data structures and architectures are being researched and developed. We will introduce an edge AI business worked on by Tokyo Artisan Intelligence Co., Ltd. (TAI), of which the presenter is the founder. Next, we will discuss implementing Vision AI, a more accurate image recognition AI model, on an FPGA. We show a SEASIDE (A Specified Edge AI SoM for Intelligence Design and Embedding) solution for an edge AI implementation. With our solution, users can realize a cost-performance effective system.

Hiroki Nakahara is a founder and CEO at Tokyo Artisan Intelligence Co., Ltd., a professor at Tohoku University, and a specific professor at Tokyo Institute of Technology.
His research interests include logic synthesis, reconfigurable architecture, embedded systems, and machine learning. He received a Ph.D. degree in computer science from the Kyushu Institute of Technology in 2007. Prof. Nakahara received the 8th IEEE/ACM MEMOCODE Design Contest 1st Place Award in 2010, the SASIMI Outstanding Paper Award in 2010, the IPSJ Yamashita SIG Research Award in 2011, the 11th FIT Funai Best Paper Award in 2012, the 7th IEEE MCSoC-13 Best Paper Award in 2013, and the ISMVL2013 Kenneth C. Smith Early Career Award in 2014. He was the Workshop Chairman for the ULSIWS from 2014 to 2017; as the Program Chairman for the HEART in 2017. In addition, due to his academic contributions, he was selected as the general chair of the FPT’23.
In 2022, the National Institute for Science and Technology Policy (NISTEP) awarded him the title of “Nice Step Researchers 2022” for his outstanding contributions to the development of science, technology, and innovation.

Start-up! Talk 2

On-sensor AI : Where data converges, AI emerges

Junyoung Park
Junyoung Park

UX Factory, Korea

UX Factory is a pioneering company dedicated to developing ASIC hardware and software solutions that revolutionized User Experience (UX) through the integration of AI technology. In the rapidly evolving landscape of artificial intelligence and edge computing, we specialize in designing cutting-edge chips that seamlessly combine CMOS Image Sensor (CIS) with AI accelerators. Our innovative solutions enable real- time data processing and enhance on-device and edge AI capabilities, setting new standards for efficiency and performance of the edge AI devices. By driving the future of intelligent devices, we offer unparalleled user experiences across a wide range of applications. In this talk, we present our on-sensor AI projects including 90nm sensor SoC chip, with results from both technical and business perspectives.

Dr. Junyoung Park is the co-founder and Chief Executive Officer (CEO) of UX Factory, Inc., a South Korea-based startup specializing in AI hardware solutions focused on next-generation AI-based user experience for edge devices. Before founding UX Factory, Dr. Park earned his B.S., M.S., and Ph.D. degrees in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, South Korea, in 2009, 2011, and 2014, respectively. Throughout his academic and professional career, he has shown a keen interest in developing customized architectures and circuits for computationally intensive algorithms, such as computer vision and deep learning, and their integration into edge platforms. Dr. Park has participated in over 10 national and international AI SoC R&D projects over the past 15 years.

Start-up! Talk 3

High-Speed SerDes IP in Data Center

Ted Shih
Ted Shih

Teletrx, Taiwan

Teletrx delivers breakthrough Serializer-Deserializer (SerDes) IP and interconnect solutions that scale bandwidth and deliver end-to-end signal integrity in next-generation platforms requiring single-lane rate up to 224Gbps & 112Gbps connectivity cross MIPI, PCIe, UCIe, and Data Center domains. Teletrx’s unique, patented DSP and mixed signal architectures are the foundation for its high performance and low power at these accelerated bandwidth rates.

Ted is the founder of Teletrx. He is responsible for the global strategy and business developments, translating Teletrx’s connectivity expertise into the advancement of global mobility solutions. This session brings together stakeholders in a discussion around the High-Speed communication in data center and also the vision of Teletrx. Before founding Teletrx, Mr. Shih has worked in IC design house and Financial companies for over 10 years and also has several startup experience. He has an extensive background in product management and subsequently progressed through a series of leadership positions including engineering team manager, director of PM department.

Start-up! Talk 4

The Importance of Area-Performance Efficiency in Computational Units

Parkson Wong
Parkson Wong

Centreon Technology, USA

Benjamin Ou
Benjamin Ou

Centreon Technology, USA

Centreon develops cutting-edge integer and floating-point computational units for use in AI, high-performance computing, and scientific computing applications. Compared to commonly-available commercial designs for floating-point adders and multipliers, we deliver comparable-to-superior performance and features (such as all-in-one units and in-path subnormal handling) using up to 39% fewer transistors, allowing computation-dense chips to pack more arithmetic units in their layout and achieve greater throughput. We know that in a computation-dense chip like a specialized AI chip, vast amounts of chip area are consumed by duplicated adders and multipliers; our units can handle multiple levels of precision and handle both integer and floating-point results with the same hardware, reducing the need for redundant units by up to 66%. We also provide fully-pipelined implementations of nonlinear functions such as the trigonometric functions, eliminating the traditional need for expensive memory accesses and lookup tables in computing such functions. Our units have been used in silicon-realized, commercial chips, such as in FuriosaAI’s Tensor Contraction Processor’s vector engine.

Parkson Wong received an M.S. in Computer Science from the University of Wisconsin-Madison, and went on to work as a Principal Scientist at the NASA Ames Research center, where he conducted research in high-end and heterogeneous computing. In the same period, he was the Principal Engineer at Silicon Graphics Inc., where he implemented and deployed high-definition video servers for major broadcast facilitating. His latest pursuit is as co-founder of Centreon Technology, where he brings four decades of computer architecture and systems design experience to achieve unparalleled performance.

Benjamin Ou received a B.A. in Computer Science and Physics from the University of California, Berkeley, during which he interned at Centreon Technology. He went on to accept a full time position with Centreon, where he initially worked on benchmarking cutting-edge hardware using standard benchmarking libraries as well as the GROMACS molecular simulation platform. Currently, he along with Parkson leads Centreon’s effort to design its own vector-capable out-of-order CPU that aims to bring the most out of Centreon’s unparalleled computational units.